@J-Jericho
excellent post you are absolutely right
Put simply, a cmos logic gate is in essence a flip flop based upon a 3.5 volt threshold
The problem is there is no such thing as a logic circuit outputting logic 1 or logic 0.
There are instead analogue circuits that output a range of voltages that we can force to behave like logic circuits.
If the voltage output of the logic circuit or gate is higher than 3.5 volt it is a logic 1 if it is less than 3.5 volts it is a logic 0. 3.5 volts has been adopted in CMOS as the threshold for logic 1
CMOS gate values are supposed to be either 0 volts or 5 volts for those logic states, but they rarely are because they are analogue circuits trying to behave like digital circuits, so we use threshold values to detect the logic states.
In realty there could be any value between those voltages and given losses in the circuits a logic 1 of above 3.5 volts could be pulled down below 3.5 volts due to a voltage sink of some kind and become a logic 0.
Then the logic has changed when it should not have changed and the computer program has then malfunctioned.
The logic state should really be unknown if the voltage in the gate output voltage is less than the 3.5 volt threshold set for logic 1, but almost 3.5 volts.
When does a 0 become a 1 at what voltage 3.50 3.49. 3.48
What happens if a gate output is at the 3.5 volt threshold and rippling slightly between 3.4 volts and 3.6 volts.
This is the computer logic equivalent of panicking.
The detection of 3.5 volts or more causes downstream logic gates to flip due to logic 1 being detected but less than 3.5 volts causes the downstream logic gate to a flop to logic 0
There is a period of indecision due to logic gate ripple where the gates are all in an indeterminate state during the ripple and they take a period of time to settle into the final state of correct logic.
The larger the number of gates the longer it takes for the ripple through and to settle
This period of settling in which the logic gates are performing illogically grows as circuits are miniaturised and with greater miniaturisation comes greater difficulty of determining logic 1 in any single gate.
The hope is of course that all logic gates will settle correctly to the correct logic value however as you quite rightly point out losses due to miniaturisation plus abnormalities can disrupt the logic gate performance.
We cannot wait forever for logic circuits to settle so we make assumptions that within a set period of time all rippling will have ceased and logic circuits will have reached the correct values.
A typical 4 logic gate cluster takes 300 ps to settle, we need not explore the ramifications of this, it is not much time, 300 trillionths of a second, but compounded by the sheer total number of logic gates in a system means that it actually can take a significant amount of time for all rippling to cease in all the gates.
This is one of the limiting factors on the growth of computer systems
After rippling has ceased we then read the output of all the gates allowing time for all rippling to end plus x, - a safety margin time. We cannot risk reading a logic gate output if it is still rippling.
But what happens when a passing neutrino enters a logic gate and trips a gate from logic 1 to logic 0 during the safety margin wait state.
Rippling must begin again. This passing neutrino could also by the way on the hard drive stab a binary value in a stored program changing the program forever and preventing the computer from obeying the designed code, because the code has now changed and is no longer as programmed.
We are bombarded by Neutrinos every day and most pass through us harmlessly but when a neutron interacts with the semiconductor material, it deposits charge, which can change the binary state of the bit and Neutrinos can only be stopped by lead or concrete so computers are vulnerable to them in stored programs in RAM in ROM and in the data carried on the bus.
We may then finish up reading the logic output during a new rippling state caused by a neutrino attack. We then have a 50 50 gamble that the logic is in error.
Exactly as you describe and pointed out J.Jericho.
And exactly as you suggest greater miniaturisation makes this effect more likely as gates miniaturise more, but neutrinos do not miniaturise and their effects could become more profound for logic circuits as we miniaturise more over time.
The more logic gates you have the more opportunity there is for Neutrino disruption.
This is a very long post I know but we are deep diving here into complex areas that usually are hidden from the general public and largely unknown to them.
The present state of miniaturisation of logic is called VLSI very large scale integration and it brings issues that are difficult to address relating to robustness and reliability of these very large scale integrated circuits.
I am comfortable J.Jericho that you already know all of this and more besides, possibly more than I do on this topic given your excellent posts.
We are in examining this topic very close to the cutting edge of computing and its far reaching implications for the future of computer systems as we plod ever onwards down the road of greater miniaturisation and with greater miniaturisation comes greater risk of failures due to the very miniaturisation that we seek.
I intended this post to illustrate exactly why your post is technically correct and on topic. I do not intend to slight other members very few people understand this stuff, and we can only know what we know.
Most members know lots of stuff I do not know and cannot hope to know and I want to make it quite clear that not knowing this deeply technical and difficult subject is no reflection on them at all.
Moores law says computer gates double in complexity every 2 years. I would suggest that Risk doubles along with that.
I am not at all surprised that most people do not know all this it is the province of micro electronics engineers largely hidden from the public and there is no need for the public to know these things only electronics engineers chip designers and systems designers need to know this stuff.
What does surprise me on a daily basis is how reliable computers are given their huge vulnerability to errors and mishap.
Computers seem to me to fly less like an F15, and more like a bumble bee, they just manage to get there despite being a bit poor at flying.